Kdjykuj

I'll preface this question by saying that I am a software developer just starting to learn the basics of electronics, so it's very likely I'm missing some fundamental intuition here.

Below is a mechanical NAND gate with two switches. I think it's supposed to be obvious that when the switches are closed, the output Q is 0 rather than 1. I don't see why this is.

I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q, so won't some current still flow to the output, putting it in a 1 state?

The intuition I'm using (which may be totally wrong) is this:

• Current acts like water gushing from V+ down all available paths.


• At a junction, current will flow through both paths in an amount inversely proportional to resistance. In this case, both paths have no additional resistance so they should split the current equally.


• The boolean equivalent of a 1 is that current is flowing through a point.

Please help me understand what I'm missing! And if you can point me to a book or online resource explaining these fundamentals, that would be very helpful. I've tried looking at a lot of "circuit tutorial" content on Google, but surprisingly haven't been able to resolve my confusion here.

The boolean equivalent of a 1 is that current is flowing through a point.

That's the fundamental confusion leading to difficulty in understanding the circuit.

Single ended logic like this encodes state as voltage not current.

Inputs of logic gates are designed to source or sink very little current, so the output of the previous stage is easily able to impose its intended voltage on the connection between output and the following input with very little current needing to flow.

Current-mode signaling does exist, but it's generally used only in noisy situations, for example the time-tested 4-20 mA current loop standard.

I also had this problem since I started learning a bit about electronics (I'm also a software engineer).

Electricity always wants to balance. If there is GND, all electricity will flow to there (actually the electrons move in reverse direction but let's ignore that for now).

This means if the switches are closed, and if Q > 0 V, all electricity will flow to GND, meaning Q will be 0 V in a very short time (read: almost instantly).

However, when one of the switches is open, the voltage from V+ will flow to Q if Q has less voltage than V+ (which is likely so), so Q will end up having the same voltage as V+.

First off the "N" means that it inverts the input the schematic is sort of doing the same but it gets off track of how the gates work. If you drew it with a relay it would make more sense

^{simulate this circuit – Schematic created using CircuitLab}

You need to study pull down and pull up resistors, the value of the resistor limits the voltage, current is not an issue really because this is all at "logic level". I had a hard time with the logic stuff at first and then all of a sudden it all made sense, good luck my friend.

I found very useful the simple description of a NAND gate to act thusly
"any zero in causes a one out".

This circuit will do that

^{simulate this circuit – Schematic created using CircuitLab}